This invention relates to a memory circuit, and more particularly to a circuit for generating a signal for activating a memory sense amplifier.
There are well known memory circuits including the single transistor type memory cell including a field effect transistor and a data storing capacitor connected serially thereto. Such a memory circuit has comprised a plurality of single transistor type memory cells arranged in rows and columns and a pair of dummy memory cells similar in construction to the memory cells and disposed in each row. For each row, the memory cells and the pair of dummy memory cells are connected in symmetrical relationship to a sense amplifier through a true bit line on the one side of the sense amplifier and a complementary bit line on the other side thereof. Further, the memory cells in each column are connected to a common word line and the dummy memory cells located on each side of the sense amplifier are connected to a common dummy word line. The word lines and dummy word lines are connected to a column decoder subsequently connected to a word line-drive generator. The column decoder is responsive to an address signal externally applied thereto to select the word line as determined by the address signal and that dummy word line located on that side of the sense amplifier remote from the selected word line. The address signal is also applied to the word line-drive generator to generate a signal for driving a word line. That signal is applied via the column decoder to the selected word line and dummy word line whereby potentials are developed on those lines until data stored on the associated capacitors are read out on the true and complementary bit lines respectively.
At that time the word line-drive generator responds to the address signal to generate an activating signal for the sense amplifier as determined by the address signal and apply it to that sense amplifier through an associated activation circuit including a series combination of a resistor, a delay circuit and another delay circuit. The sense amplifier selected by the address signal amplifies a potential difference between potentials developed on the mating bit lines in response to the activating signal applied thereto.
However each of the word lines and dummy word lines includes a parasitic resistance and a parasitic capacitance having high magnitudes so that the rise of the potentials in the selected word line and dummy word line are fairly delayed with respect to that of the word line-drive signal and has a gentle slope as compared with the latter signal. Therefore it has been difficult to determine a level at which the associated capacitors are read out on the true and complementary bit lines. In order to avoid this difficulty, the resistor has been connected in the activation circuit to optimalize a timing of activation of the sense amplifier. Alternatively the two delay circuits might be strictly designed and constructed without the resistor. This has attended with troublesome jobs. Also conventional memory circuits such as described above have disadvantageously required large-sized semiconductor chips and been easily affected by a variation in manufacturing process.
Accordingly it is an object of the present invention to provide an improved memory circuit including a sense amplifier capable of being easily activated at the optimum timing and prevented from malfunctioning due to a variation in manufacturing process without increasing an area of a semiconductor chip involved.